The present invention relates to an arithmetic operation circuit containing a plurality of arithmetic cells which is fabricated in an integrated manner.
In a prior art arithmetic operation circuit, e.g. a multiplication and division circuit for performing a multiplication and a division described by D. P. Agrawal "High-Speed Arithmetic Arrays", IEEE trans. Comput. vol. C-28, No. 3, March 1979, pages 214-224, arithmetic cells within the multiplication/division circuit include only adders. In the circuit, a subtracting process in a division is a twos-complement adding operation. Therefore, Agrawal's multiplication/division circuit described in IEEE has an advantage in that power consumption is low and an operation delay time is small, compared with a multiplication/division circuit of which the arithmetic cells each comprise an adder and a subtractor. In Agrawal's circuit, a carry process is performed by a so-called restoring technique. Therefore, time taken for the carry process is short and an arithmetic operation is performed at high speed and high precision.
In the arithmetic operation circuit described in Agrawal, however, when binary numbers of 16 bits are multiplied by each other or a binary number of 31 bits (dividend) is divided by a binary number of 16 bits (divisor), 271 arithmetic cells are required to be arranged in a repetitive fashion. Each of the arithmetic cells includes 18 MOS gates. Therefore, the arithmetic operation circuit includes totally 4,878 MOS gates.
Assume that those MOS gates are enhancement/depletion type MOS gates (E/D type MOS gates), and that half of the whole gates are equivalently held in an ON state for calculating the power consumption of the arithmetic operation circuit when it is executing an ordinary operation. On this assumption, current flowing through a single gate is approximately 0.1 mA. Accordingly, the total current consumed by the arithmetic operation circuit is increased up to approximately 244 mA, resulting in an increase of the power consumption in the arithmetic operation circuit. This leads to an undesirable phenomenon, e.g., increase of the heat generated in the operation. The increase of the heat makes it difficult to integrate the arithmetic operation circuit also containing a peripheral circuit such as resistors and a control circuit into a substrate of one chip.
Conversely, when all the gates in Agrawal's arithmetic operation circuit are not the E/D type MOS gates but are complementary type MOS gates (CMOS gates), the total of the power consumption is reduced. The subjective characteristic of the C-MOS gate, however, brings about decrease of the operation speed, increase of the carry operation time, and hence increases the time required for the whole arithmetic operation. Furthermore, a degree of integration of the circuit is reduced, so that an area of one chip substrate increases.